2025 Keynote Speakers

Joe Parks, PhD

Vice President, Technology Development

Intel Corporation

Joe Parks, PhD, is the Vice President of Technology Development and Director of Intel’s Oregon Assembly Test Development Factory located in Portland, Oregon. His team is chartered to develop and deliver Intel’s cutting-edge Advanced Packaging and pre-assembly test technologies. These disaggregated wafer-level assembly technologies include 2.5D Embedded Bridge (EMIB), 3D solder-based Foveros die stacking technology, and 3D-3.5D Hybrid Bond Cu-Cu sub-10um interconnect technology. Additionally, his team develops all of Intel’s pre-packaged test processes including Automated Test Equipment, probing solutions, thermal control systems, probe card development and design, and factory automation. Notably, this includes Intel’s Singulated Die Test systems.

The OATD factory is a fully automated facility encompassing over 150k sq-ft of manufacturing space and generically supports process development, engineering samples, and initial ramp of both Intel and Foundry products. Joe has the honor of managing a highly competent, technical, and diverse team comprised of approximately 1400 people.

Known Good Die as a Key Enabler for Advanced Packaging in a Disaggregated World

Heterogeneous integration, or disaggregation, is quickly gaining importance as a means to drive Moore’s Law. Larger and more complex packages with a multitude of die, interposers, and silicon bridges are becoming prominent in segments like AI and HPC. Integrating multiple chiplets and creating complex die stacks via technologies such as Hybrid Bonding drives the need for true Known Good Die (KGD) validation prior to chip attach and package assembly. KGD improves yield and saves significant cost. As such, Sort has never been more critical to the Semiconductor industry as a means of screening bad chiplets via the shift of structural and functional content, as well as stress, upstream in the product’s manufacturing flow. Sort has always provided process feedback to the fab or foundry, but now has an additional role to play in providing timely and critical Wafer Level Assembly feedback. Intel has heavily leveraged advanced Sort, demonstrating significant yield and cost savings across multiple product segments with a first of a kind Singulated Die Sort (SDx) platform which enables testing die and die stacks with a unique and advanced thermal control system in High Volume Manufacturing. Advanced thermal control at Sort greatly improves the effectiveness of stress testing, enables a test content shift left and performance binning of die, and has a profound impact on the capture or attach rate of die to complex packages. Enabling test at the die and die stack level allows Wafer Bump, Die Prep, and Wafer Level Assembly health monitoring and yield learnings to pull in by months in the early critical stages of product development. Intel’s Die Sort capability is leading the way to enabling Known Good Die and Known Good Die Stacks to support advanced packaging and the disaggregated, chiplet future.