Schedule-At-A-Glance

Start
7:00
7:30
8:00
8:30
9:00
9:30
10:00
10:30
11:00
11:30
12:00
12:30
13:00
13:30
14:00
14:30
15:00
15:30
16:00
16:30
17:00
17:30
18:00
18:30
19:00
19:30
20:00
20:30
SWTEST Golf Tournament
Golfers Breakfast (Valley Promenade)
William Mann Memorial Golf Tournament (Omni La Costa Golf Resort - Starter Area - Legends course)
 
Registration
 
Conference Registration Check-In (Costa de la Luna Foyer)
 
Attendees Welcome Mixer (Bar Traza)
 

Start
7:00
7:30
8:00
8:30
9:00
9:30
10:00
10:30
11:00
11:30
12:00
12:30
13:00
13:30
14:00
14:30
15:00
15:30
16:00
16:30
17:00
17:30
18:00
18:30
19:00
19:30
20:00
20:30
21:00
21:30
22:00
22:30
EXPO day 1 (Costa Del Sol)
Exhibitor Check-In (Costa de la Luna Foyer)
Exhibitor Setup (Costa Del Sol Ballroom)
 
EXPO Open (Costa Del Sol Ballroom)
Sponsor Hospitality Events
 

Start
7:00
7:30
8:00
8:30
9:00
9:30
10:00
10:30
11:00
11:30
12:00
12:30
13:00
13:30
14:00
14:30
15:00
15:30
16:00
16:30
17:00
17:30
18:00
18:30
19:00
19:30
20:00
20:30
21:00
21:30
22:00
22:30
Poster Day 2 (Costa de la Luna Foyer)
 
Poster Session (Costa de la Luna Foyer)
 
EXPO day 2 (Costa Del Sol)
Conference Registration Check-In (Costa de la Luna Foyer)
 
SWT Crew Mixer (Costa Del Sol Side Lawn)
EXPO Open / Reception (Costa Del Sol Ballroom)
Sponsor Hospitality Events
 

Start
7:00
7:30
8:00
8:30
9:00
9:30
10:00
10:30
11:00
11:30
12:00
12:30
EXPO day 3 (Costa Del Sol)
Exhibitor Teardown (Costa Del Sol Ballroom)
 

Detailed Schedule

Time Event
7:00 - 8:00
Golfers Breakfast (Valley Promenade)
8:00 - 13:30
William Mann Memorial Golf Tournament (Omni La Costa Golf Resort - Starter Area - Legends course)
13:00 - 17:00
Conference Registration Check-In (Costa de la Luna Foyer)
17:30 - 20:00
Attendees Welcome Mixer (Bar Traza)

Time Event
7:00 - 8:00
Speakers' Breakfast (Las Palmas 1 and 2)
7:00 - 8:00
Continental Breakfast (Costa de la Luna Courtyard/Lawn)
7:00 - 16:00
Conference Registration Check-In (Costa de la Luna Foyer)
7:00 - 12:00
Exhibitor Check-In (Costa de la Luna Foyer)
8:00 - 9:15
Poster Setup
8:00 - 8:15
Welcome to SWTEST San Diego
Jerry BROZ (SWTest Conference, USA)
8:15 - 9:15
Speaker Headshot
Keynote Speaker
Known Good Die as a Key Enabler for Advanced Packaging in a Disaggregated World
Intel Corporation - USA
9:15 - 10:00
Coffee Break and Poster Session
10:00 - 12:00
Session 1: RF Applications
Session Chair: Raffaele VALLAURI (Technoprobe SpA, Italy)
10:00 - 10:30
Narrow Pitch Impedance Standard Substrates (ISS) for Pyramid Probe Applications
Pratik GHATE (FormFactor, Inc. - USA)
Presenter Headshot
10:30 - 11:00
Characterization of High Performance RF Vertical Probe Heads
Daniel BOCK (Probe Test Solutions Limited - USA)
Presenter Headshot
11:00 - 11:30
Next Generation Probe Card Design for 112Gbps PAM4 Test Solution
Johnson TSENG (Chunghwa Precision Test Tech. Co., Ltd. - USA), Jhih-Hong CHENG, Kimmie CHEN (Chunghwa Precision Test Tech. Co., Ltd. - Taiwan)
Presenter Headshot
11:30 - 12:00
Risk Mitigation Strategies for mmWave Production Test Environments
Kevin AYERS, Ryan GARRISON (FormFactor, Inc. - USA)
Presenter HeadshotPresenter Headshot
12:00 - 16:00
Exhibitor Setup (Costa Del Sol Ballroom)
12:00 - 13:30
Lunch
13:30 - 15:00
Session 2: Optical Device Testing Challenges
Session Chair: Mark OJEDA (Infineon Semiconductor, USA)
13:30 - 14:00
Probe Heads for Optical Wafer-Level Testing
Philipp DIETRICH, Andrés MACHADO, Florian RUPP (Keystone Photonics GmbH - Germany)
Presenter Headshot
14:00 - 14:30
Novel direct probe solution for opto-electronic wafer-level PIC testing
Golam BAPPI (Ayar Labs - USA), Tobias GNAUSCH (Jenoptik Optical Systems GmbH - Germany)
Presenter HeadshotPresenter Headshot
14:30 - 15:00
Optical edge coupling method for fully automated PIC wafer-level testing
Anna PECZEK (IHP Leibniz- Institut f. innovative Mikroelektronik - Germany), Dan RISHAVY (FormFactor, Inc. - USA)
Presenter HeadshotPresenter Headshot
15:00 - 15:30
Coffee Break and Poster Session
15:30 - 17:00
Session 3: Probe Potpourri
Session Chair: Davide APPELLO (Technoprobe SpA, Italy)
15:30 - 16:00
Probing Technologies for KGD Testing: Choosing Between Needle Probes and Pogo Pins
Michael LAWSON, Luca FANELLI, Sara MONFREDA (SPEA S.p.A. - Italy)
Presenter Headshot
16:00 - 16:30
Newly developed low CTE LTCC material for ST substrates
Noriyuki YOSHIDA, Eiichi NAKAMURA, Shigekatsu KONO, Takahisa YAMAGUCHI (Nippon Electric Glass Co., Ltd. - Japan)
Presenter Headshot
16:30 - 17:00
Advanced Packaging from a probe card suppliers’ perspective
Gabriela PEREIRA (Yole Group - France), John WEST (Yole Group - United Kingdom)
Presenter Headshot
17:00 - 20:00
EXPO Open (Costa Del Sol Ballroom)
17:00 - 20:00
Speakers' Corner (Costa Del Sol Ballroom)
20:00 - 22:00
Sponsor Hospitality Events

Poster Sessions

Poster Session (Costa de la Luna Foyer)

Session Chair: John CALDWELL (MJC Electronics Corporation, USA)
  • Machine learning based wafer sort yield prediction based on wafer acceptance test data
    Yin Hong CHAN, Amalini MANSOR, Changqing CHEN, Jia Yi CHUA, Man Hon THOR, Yong Keong TEOH (GlobalFoundries - Singapore)
  • Advancing ATE with ElevATE’s Modular Silicon Strategy
    Kurt ERIKSON (Elevate Semiconductor - USA)
  • Known Good Die - Best Practice for Probing High Power Devices
    Sebastian SALBRECHTER, Diana DAMIAN, Rainer GAGGL (T.I.P.S. Messtechnik GmbH - Austria)
  • On Probe Card Cleaning: The Interplay of Materials Science and Tribology​
    Brian GREEN, Kenneth BOBLAK (Entegris - USA)
  • A comparison of Nanosecond, Picosecond and Femtosecond laser sources and their manufacturing capabilities in Guide Plate production
    Chris STOKES, Greg HARRIS, Dimitris KARNAKIS, Tuohy SIMON (Oxford Lasers Ltd - United Kingdom)
  • Enhancing Interposer Design for High Pin Count Probe Cards
    Jay KIM (OKins Electronics - USA)
  • Enhancing High-Speed Testing Performance of RF Probe Cards through Low Dielectric Polyimide Materials
    TAE KYUN KIM, YONG HO CHO, YOO SEOK JUNG (Protec MEMS Technology - South Korea)
  • Automation of Large and Heavy Probe Card Exchange, Handling and Storage
    Benedikt PONGRATZ (Turbodynamics - USA)

Poster Session (Costa de la Luna Foyer)

Session Chair: John CALDWELL (MJC Electronics Corporation, USA)

    Time Event
    7:00 - 15:00
    Conference Registration Check-In (Costa de la Luna Foyer)
    7:00 - 8:00
    Committee Breakfast (Las Palmas 1 and 2)
    7:00 - 8:00
    Continental Breakfast (Costa de la Luna Courtyard/Lawn)
    8:00 - 8:15
    SWT Crew Update
    Karen ARMENDARIZ (Celadon Systems, USA)
    8:15 - 9:15
    Speaker Headshot
    Keynote Speaker
    Packaging Trends in the Power Semiconductor Market
    Wolfspeed, Inc. - USA
    9:15 - 10:00
    Coffee Break and Poster Session
    10:00 - 12:00
    Session 4: RF, High Volume-Test and Advanced Applications
    Session Chair: Michael HUEBNER (FormFactor, USA)
    10:00 - 10:30
    Towards Ultra-High Pin Count Probe Card for high end logic devices
    Alice GHIDONI, Elia MISSAGLIA (Technoprobe SpA - Italy)
    Presenter HeadshotPresenter Headshot
    10:30 - 11:00
    Advanced Probe Card Solutions to address HBM wafer and stacked die test challenges.
    David COOKE, Kalyanjit GHOSH (FormFactor, Inc. - USA)
    Presenter HeadshotPresenter Headshot
    11:00 - 11:30
    When wafer test probes meet Femtosecond Laser micro cutting and turning
    Valentin BEUCHAT (Posalux SA - Switzerland)
    Presenter Headshot
    11:30 - 12:00
    Anisotropy in High-Strength Palladium Alloys for Foil Probe Applications
    Patrick BOWEN, Grant JUSTICE, Megan PUGLIA (Deringer-Ney Inc - USA)
    Presenter Headshot
    12:00 - 13:30
    Lunch
    12:00 - 13:30
    Poster Removal
    13:30 - 15:00
    Session 5: Temperature Testing Challenges
    Session Chair: Rey RINCON (SWTest Conference, USA)
    13:30 - 14:00
    Singulated Die Sort as a tool to enable high precision thermal control during high-volume manufacturing
    Jaime SANCHEZ, Matthew ZEMAN (Intel Corporation - USA)
    Presenter Headshot
    14:00 - 14:30
    Challenges of Heat Generation in Probe Cards
    Kurt GUTHZEIT, Emmett RICKS (Micron - USA)
    Presenter Headshot
    14:30 - 15:00
    300mm Probe card for Logic device with wide temperature range testing
    Dong Il KIM, Choong Sik KIM, Il Du KIM, Jin Hyang HEO (AMST Co. - South Korea), Mark OJEDA, Phuc DO (Infineon Technologies AG - USA)
    Presenter Headshot
    15:30 - 17:00
    SWT Crew Mixer (Costa Del Sol Side Lawn)
    17:00 - 20:00
    Speakers' Corner (Costa Del Sol Ballroom)
    17:00 - 20:00
    EXPO Open / Reception (Costa Del Sol Ballroom)
    20:00 - 22:00
    Sponsor Hospitality Events

    Poster Sessions

    Poster Session (Costa de la Luna Foyer)

    Session Chair: John CALDWELL (MJC Electronics Corporation, USA)
    • Machine learning based wafer sort yield prediction based on wafer acceptance test data
      Yin Hong CHAN, Amalini MANSOR, Changqing CHEN, Jia Yi CHUA, Man Hon THOR, Yong Keong TEOH (GlobalFoundries - Singapore)
    • Advancing ATE with ElevATE’s Modular Silicon Strategy
      Kurt ERIKSON (Elevate Semiconductor - USA)
    • Known Good Die - Best Practice for Probing High Power Devices
      Sebastian SALBRECHTER, Diana DAMIAN, Rainer GAGGL (T.I.P.S. Messtechnik GmbH - Austria)
    • On Probe Card Cleaning: The Interplay of Materials Science and Tribology​
      Brian GREEN, Kenneth BOBLAK (Entegris - USA)
    • A comparison of Nanosecond, Picosecond and Femtosecond laser sources and their manufacturing capabilities in Guide Plate production
      Chris STOKES, Greg HARRIS, Dimitris KARNAKIS, Tuohy SIMON (Oxford Lasers Ltd - United Kingdom)
    • Enhancing Interposer Design for High Pin Count Probe Cards
      Jay KIM (OKins Electronics - USA)
    • Enhancing High-Speed Testing Performance of RF Probe Cards through Low Dielectric Polyimide Materials
      TAE KYUN KIM, YONG HO CHO, YOO SEOK JUNG (Protec MEMS Technology - South Korea)
    • Automation of Large and Heavy Probe Card Exchange, Handling and Storage
      Benedikt PONGRATZ (Turbodynamics - USA)

    Time Event
    7:00 - 10:00
    Exhibitor Teardown (Costa Del Sol Ballroom)
    7:00 - 8:00
    Continental Breakfast (Costa de la Luna Courtyard/Lawn)
    8:00 - 9:30
    Session 6: New Probe Materials
    Session Chair: Jerry BROZ (SWTest Conference, USA)
    8:00 - 8:30
    Fully integrated probes made by µ3D printing for customizable, fine-pitch test solutions
    Edgar HEPP, Wabe KOELMANS, Francesco COLANGELO, Patrik SCHüRCH (Exaddon - Switzerland), Mathieu ACHARD, Raphaël RUETSCH (Synergie Cad - France), Sam LIN (Xsquare - Taiwan)
    Presenter Headshot
    8:30 - 9:00
    Unlocking Secrets: Enhancing Semiconductor Testing with Pd-Cu-Ag Alloys
    Lea LUMPER, Verena MAIER-KIENER (Montanuniversität Leoben - Austria), Andreas STARK (Helmholtz-Hereon - Germany)
    Presenter Headshot
    9:00 - 9:30
    Digital Lithography Enhances Fine Pitch Probe Cards Performance
    Ksenija VARGA, Holly ROMAN, Uhrmann THOMAS, Zenger TOBIAS (EV Group - Austria), Janssen DIMITRI, Reybrouck MARIO, Van Herck NIELS, Vanclooster STEFAN, Vandevyvere MARIEKE (Fujifilm Electronic Materials - Belgium)
    Presenter Headshot
    9:30 - 10:00
    Break
    10:00 - 11:30
    Session 7: Process Optimization
    Session Chair: Patrick MUI (JEM America, USA)
    10:00 - 10:30
    Spike Safe Floating VI Design & Associated FET Testing Methods
    Ramana TADEPALLI (Texas Instruments - USA)
    Presenter Headshot
    10:30 - 11:00
    Study of contamination and key parameters in wafer probe card testing.
    Cédric HERMET (STMicroelectronics - France), Salvatore DE SIENA (Technoprobe SpA - Italy)
    Presenter HeadshotPresenter Headshot
    11:00 - 11:30
    Probe technologies compared - introducing TIPS' new RzBeam and a universal metric for scrub
    Diana DAMIAN, Georg FRANZ (T.I.P.S. Messtechnik GmbH - Austria)
    Presenter HeadshotPresenter Headshot
    11:30 - 11:45
    Awards Presentations
    Jerry BROZ (SWTest Conference, USA)
    11:45 - 12:00
    Conference Adjourns

    Keynote Information

    Monday Keynote Speaker

    Speaker Headshot

    Joseph PARKS, PhD

    Intel Corporation - USA

    Joe Parks, PhD, is the Vice President of Technology Development and Director of Intel's Oregon Assembly Test Development Factory located in Portland, Oregon. His team is chartered to develop and deliver Intel's cutting-edge Advanced Packaging and pre-assembly test technologies. These disaggregated wafer-level assembly technologies include 2.5D Embedded Bridge (EMIB), 3D solder-based Foveros die stacking technology, and 3D-3.5D Hybrid Bond Cu-Cu sub-10um interconnect technology. Additionally, his team develops all of Intel’s pre-packaged test processes including Automated Test Equipment, probing solutions, thermal control systems, probe card development and design, and factory automation. Notably, this includes Intel’s Singulated Die Test systems.

    Keynote Topic:

    Known Good Die as a Key Enabler for Advanced Packaging in a Disaggregated World

    Heterogeneous integration, or disaggregation, is quickly gaining importance as a means to drive Moore’s Law. Larger and more complex packages with a multitude of die, interposers, and silicon bridges are becoming prominent in segments like AI and HPC. Integrating multiple chiplets and creating complex die stacks via technologies such as Hybrid Bonding drives the need for true Known Good Die (KGD) validation prior to chip attach and package assembly. KGD improves yield and saves significant cost. As such, Sort has never been more critical to the Semiconductor industry as a means of screening bad chiplets via the shift of structural and functional content, as well as stress, upstream in the product’s manufacturing flow. Sort has always provided process feedback to the fab or foundry, but now has an additional role to play in providing timely and critical Wafer Level Assembly feedback. Intel has heavily leveraged advanced Sort, demonstrating significant yield and cost savings across multiple product segments with a first of a kind Singulated Die Sort (SDx) platform which enables testing die and die stacks with a unique and advanced thermal control system in High Volume Manufacturing.  Advanced thermal control at Sort greatly improves the effectiveness of stress testing, enables a test content shift left and performance binning of die, and has a profound impact on the capture or attach rate of die to complex packages. Enabling test at the die and die stack level allows Wafer Bump, Die Prep, and Wafer Level Assembly health monitoring and yield learnings to pull in by months in the early critical stages of product development. Intel’s Die Sort capability is leading the way to enabling Known Good Die and Known Good Die Stacks to support advanced packaging and the disaggregated, chiplet future.


    Tuesday Keynote Speaker

    Speaker Headshot

    Joseph ROYBAL, Mr.

    Wolfspeed, Inc. - USA

    Joseph Roybal is the Senior Vice President of Global Backend Operations at Wolfspeed aligning backend manufacturing roadmaps, production strategies, and capital allocation to scale efficiently with Wolfspeed’s exponential growth. He leads an expanding worldwide team focused on systemic manufacturing solutions, SiC package innovation, strategic partnerships with OSATs, and effective product manufacturing solutions for all Wolfspeed businesses and major SiC backend operations.

    Keynote Topic:

    Packaging Trends in the Power Semiconductor Market

    High Voltage (HV) power semiconductors play a critical role in the mass commercialization of electrical vehicles. Silicon carbide (SiC) based MOSFET’s have become commonplace as a superior alternative to silicon devices in HV applications.  While this shift to SiC devices results in significant attention on wafer substrates, epitaxial layers, and front end technology, it also results in increased focus on backend packaging requirements. Silicon carbide devices run at a higher junction temperature compared to silicon devices, which drives unique packaging trends and roadmaps.