Schedule-At-A-Glance

Start
19:00
19:30
20:00
20:30
21:00
21:30
22:00
22:30
23:00
23:30
EXPO Carry-In/Setup
 
EXPO Carry-In/Setup from 10/23 20:00 to 23:00
 

Start
7:00
7:30
8:00
8:30
9:00
9:30
10:00
10:30
11:00
11:30
12:00
12:30
13:00
13:30
14:00
14:30
15:00
15:30
16:00
16:30
17:00
17:30
18:00
18:30
19:00
19:30
20:00
20:30

Start
7:00
7:30
8:00
8:30
9:00
9:30
10:00
10:30
11:00
11:30
12:00
12:30
13:00
13:30
14:00
14:30
15:00
15:30
16:00
16:30
17:00
17:30
18:00
18:30
19:00
19:30
20:00
20:30
21:00
21:30
Poster (Grand Foyer 1st floor)
 
Poster Session
 
Poster Session
 
Tech Showcase (Navis C 1st Floor)
 
MJC
 
Teraprobe:
 
EXPO (ARGOS C-F 1st Floor)
 
EXPO Open
EXPO Move-out
 
Japanese Street Food Festival (Olive/Garden 5th Floor)
 

Start
5:30
6:00
6:30
7:00
7:30
8:00
8:30
9:00
9:30
10:00
10:30
11:00
11:30
12:00
12:30
13:00
13:30
14:00
14:30
15:00
15:30
16:00
16:30
17:00
Charity Golf Tournament and Networking
2024 SWTest Asia Charity Golf Tournament (The Classic Golf Club)
 

Detailed Schedule

Time Event
20:00 - 23:00
EXPO Carry-In/Setup from 10/23 20:00 to 23:00

Time Event
7:30 - 9:30
EXPO Move-in
7:30 - 17:30
Attendees Registration Check-In
8:45 - 9:15
Fukuoka Governor Welcome
Jerry BROZ (SWTest Conference Chair, USA)
9:15 - 10:00
Speaker Headshot
Visionary Keynote
Silicon Seabelt 2.0: Challenges of Kyushu for Reproduction of Silicon Island
National Institute of Information - Japan
10:00 - 10:30
Break
10:00 - 10:30
Poster Session
Nyi Nyi THEIN (Western Digital Corporation , Japan)
10:00 - 17:30
EXPO Open
10:30 - 12:00
Session 1 Practical Test Solutions from MEMS, Power, and Optical
Session Chair: Eric Chia-Cheng CHANG (Intel, USA)
10:30 - 11:00
Novel True-Kelvin MEMS Analytical DC Probes to enable Accurate and Repeatable Characterization of Advanced-Node devices for AI applications
Choon Beng SIA (FormFactor Inc - Singapore), Masa WATANABE (FormFactor Japan - Japan)
Presenter HeadshotPresenter Headshot
11:00 - 11:30
Consideration of Resistance with Shared Power line for High Current device
Shoichi MATSUO (Micron Memory Japan Inc. - Japan)
Presenter Headshot
11:30 - 12:00
From Lab to Line: Enabling Efficient PIC Testing for Mass Production
Andrew YICK, Andy CHANG, Calvin YANG, Supreet KHANAPET (Marvell - USA), Christian KARRAS, Tobias GNAUSCH (Jenoptik - Germany)
Presenter Headshot
12:00 - 14:00
Lunch
14:00 - 15:30
Session 2 Innovative Testing Solutions for High-Performance Devices
Session Chair: Clark LIU (MJC Taiwan, Taiwan)
14:00 - 14:30
Addressing High-Speed Devices: Strengthening and Advancing MEMS Probe Cards
Masataka KIMOTO (MICRONICS JAPAN CO.,LTD - Japan), Yuka HOMAN (MICRONICS JAPAN CO.,LTD. - Japan), Shinji TANAKA (MICRONICS JAPAN - Japan)
Presenter HeadshotPresenter Headshot
14:30 - 15:00
A novel memory test system with an electromagnet for STT-MRAM wafer level testing
Masaharu TSUTA (Tohoku University - Japan), Masatomo TAKAHASHI (Accretech - Japan)
Presenter Headshot
15:00 - 15:30
100+K Ultra HIGH Pin Count Probe Card
Zach HSIEH (MPI Corporation - Taiwan)
Presenter Headshot
15:30 - 16:00
Break
15:30 - 16:00
Poster Session
Nyi Nyi THEIN (Western Digital Corporation , Japan)
16:00 - 17:30
Session 3 Challenges of Advanced Devices and Complex Systems
Session Chair: Alan FERGUSON (Oxford Lasers, United Kingdom)
16:00 - 16:30
A Cost-Effective Test Solution for Parametric Test & Reliability Lab
Adam KONICEK (Celadon Systems, Inc. - USA), Ching Too CHEN, Jeff GRUSZYNSKI, Chintankumar PATEL, Jocelyn HSIEH, Jonathon LEE (Chroma ATE, Inc. - USA)
Presenter HeadshotPresenter HeadshotPresenter Headshot
16:30 - 17:00
Automated Test Equipment for Battery Management Systems: Challenges and Solutions
Sandeep D'SOUZA (Elevate Semiconductor - USA)
Presenter Headshot
17:00 - 17:30
Probing challenge New MEMS probe design to control probe creep/fatigue for high temp probing.
Hiroki KITAMURA, Tomonao NAKASHIMA (Japan Electronic Material Corp - Japan)
Presenter HeadshotPresenter Headshot
17:30 - 20:00
Kagamiwari Ceremony & Welcome Reception

Poster Sessions

Poster Session

Session Chair: Nyi Nyi THEIN (Western Digital Corporation , Japan)
  • Advanced DUT protection during Avalanche testing on wafer level
    Ondrej BETAK, Zdenek SIMERSKY (UNITES Systems a.s. - Czech Republic)
  • More effective high voltage(1,000V) parametric test technique with MEMS probe card
    Takao SAEKI (FormFactor Inc - Japan)
  • New Cleaning Sheet filled with abrasive gel in all cells of melamine sponge.
    Tad ROKKAKU (Probe Innovation USA, LLC - USA)
  • Towards Ultra-High Pin Count Probe Card for high end logic devices
    Alice GHIDONI, Elia MISSAGLIA (Technoprobe Spa - Italy)
  • Adjusting Device Temperature Measurement using a Thermocouple Probe Card
    Hiroyuki NAKAMURA (Nidec SV Probe - Japan)
  • Power supply characteristics of Printed Wiring Boards for low-voltage, high-speed device testing
    Wai Kit K (Lincstech Co., Ltd. - Japan)
  • Enhancing High-Density Semiconductor Testing with Dual-Head Laser Micro Bonding and Vacuum Gripper Technology
    Gi Jung NAM, HONG CHUL KIM (DAWON NEXVIEW - South Korea)
  • A Comprehensive Study on Improving Probe Card Transmission Lines for Effective High-Frequency Wafer-Level Testing
    Alessia GALLI, Dario VILLA (Technoprobe - Italy)
  • New Flying Probe Tester for Probe Cards
    Koichi ANDO (HIOKI E.E. CORPORATION - Japan)
  • Development of low CTE LTCC material for ST substrates
    Takahisa YAMAGUCHI, Eiichi NAKAMURA, Noriyuki YOSHIDA, Shigekatsu KONO (Nippon Electric Glass Co.,Ltd. - Japan)
  • Introduction of precious metal alloy for Probe-pins materials and mechanical properties of Cu-Ag alloy that product name called TK-101.
    Tetsuya KATO, Suganuma RYOSUKE, Takada KAZUYASU (TANAKA KIKINZOKU KOGYO K.K. - Japan)
  • Testing AI chips and KGD at wafer-level: A new approach for full content test in wafer probing
    Klemens REITINGER (ERS electronic GmbH - Germany)
  • Productivity Enhancements when Drilling Guide Plates for Advanced Vertical Probe Cards - A Comparison between Nanosecond, Picosecond and Femtosecond Pulsed Lasers
    Alan FERGUSON, Chris STOKES (Oxford Lasers - United Kingdom)
  • ATE Spring Pin to DUT Board Via Interconnect: Myths and Challenges
    Jose MOREIRA (Advantest - Germany)
  • Wafer test with simultaneous stimulation of sensor devices
    Georg FRANZ (T.I.P.S. Messtechnik GmbH - Austria)
  • Process for Integrating MLOs Manufactured on Digital Lithography Systems
    Ksenija VARGA, R HOLLY, T UHRMANN, T ZENGER (EV Group - Austria), C LEE, Y KUO (EV Group - Taiwan), C WANG, H CHANG, L CHANG, T YANG (ITRI Industrial Technology Research Institute - Taiwan), D JANSSEN, M REYBROUCK, M VANDEVYVERE, N VAN HERCK, S VANCLOOSTER (FUJIFILM Electronic Materials (Europe) - Belgium)
  • Hybrid Bonding Technology for Next-Generation 3D-IC/Chiplets
    Takafumi FUKUSHIMA, Fukushima TAKAFUMI (Tohoku University - Japan)
  • 3D-IC Fabrication with TSV at the die level from 2D-IC
    Jiayi SHEN, Jlayi SHEN (Tohoku University - Japan)
  • Robust Classifications of WBM Defect Patterns -Multimodal approach 
    Taiki AI, Daisuke TAKADA, Koichi SUMIYA, Sumika ARIMA, Taiki ITO, Takumi MAEDA (University of Tsukuba - Japan)
  • Interaction Modeling of High-dimensional Data with the Bias and High Correlation -Sparse Factorization Machines Approach.
    Haruki OZAWA, Sara HOSHINO, Sumika ARIMA, Sumika WATANABE, Taiki ITO, Takuya MATSUZAWA (University of Tsukuba - Japan)

Poster Session

Session Chair: Nyi Nyi THEIN (Western Digital Corporation , Japan)

    Time Event
    7:30 - 17:00
    Attendees Registration Check-In
    8:45 - 9:00
    Friday Overview
    Jerry BROZ (SWTest Conference Chair, USA)
    9:00 - 9:30
    Speaker Headshot
    Keynote Speaker
    Critical Role of Test for Image Sensor Development
    Sony Corporation - Japan
    9:30 - 10:00
    Speaker Headshot
    Keynote Speaker
    New Wafer Testing Challenges for Leading-Edge SoC Products
    Socionext Inc. - Japan
    10:00 - 10:30
    Break
    10:00 - 10:30
    Poster Session
    Nyi Nyi THEIN (Western Digital Corporation , Japan)
    10:00 - 16:00
    EXPO Open
    10:30 - 12:00
    Session 4 Advancing Wafer Probing Efficiency and Quality
    Session Chair: Masatomo TAKAHASHI (Accretech, Japan)
    10:30 - 11:00
    Quantum Computing IC Die Level Test Solution at mK-temperature Environment
    Alan LIAO (FormFactor - USA), Takuji MIKI (Kobe University - Japan)
    Presenter HeadshotPresenter Headshot
    11:00 - 11:30
    Cleaning Innovations to Maximize OEE for High Volume Memory Test
    Victoria TRAN (Gel-Pak - USA), Tomonao NAKASHIMA (Japan Electronic Material Corp - Japan)
    Presenter Headshot
    11:30 - 12:00
    Improvement of probe-to-wafer contact resistance for inline automated testing for different technologies
    Anton GAVRILOV, Geert GOUWY, Van Dievel MARC, Vercaigne GREGOR (Imec - Belgium)
    Presenter Headshot
    12:00 - 14:00
    Lunch
    14:00 - 15:30
    Session 5 High-Speed KGD and Power Module Testing Challenges
    Session Chair: Alex YANG (MPI Corporation, Taiwan)
    14:00 - 14:30
    “Challenges and Solutions in Wafer Testing” from the Perspective of Power Semiconductor Back-End Processes and Modules
    Kai SUZUKI, Masashi HOSHINO, Nobuyuki TOYODA (TESEC Corporation - Japan), Kiyotaka YAMANISHI, Masatomo TAKAHASHI, Naoya TAKEUCHI (Accretech - Japan), Noriyuki IWAMURO (University of Tsukuba - Japan)
    Presenter HeadshotPresenter Headshot
    14:30 - 15:00
    Enhancing Reliability and Accuracy in High-Speed KGD Testing through Comprehensive System Improvements
    Dario VILLA (Technoprobe - Italy), Giulia ROTTOLI (Technoprobe Spa - Italy)
    Presenter HeadshotPresenter Headshot
    15:00 - 15:30
    Accomplishing True Known Good Die Verification Testing in Wafer Test
    Kosuke YAMANISHI (Tokyo Electron Ltd. - Japan), Yuki HIROSE (Tokyo Electron Technology Solutions Ltd. - Japan)
    Presenter HeadshotPresenter Headshot
    15:30 - 16:00
    Break
    15:30 - 16:00
    Poster Session
    Nyi Nyi THEIN (Western Digital Corporation , Japan)
    16:00 - 17:30
    Session 6 Probe Card MLO and PCB Design for High-Speed
    Session Chair: Nobuhiro KAWAMATA (FormFactor, Japan)
    16:00 - 16:30
    Space Transformer Organic Technologies for Next-Generation Probe Card Substrates
    Yo NOZAKA (FICT Limited - Japan)
    Presenter Headshot
    16:30 - 17:00
    On PCB with 50Gbps for ATE board, Characteristic improvement Approach
    Takahiro YAGI (OKI Circuit Technology Co., Ltd. - Japan)
    Presenter Headshot
    17:00 - 17:30
    Mechanical Modeling and Simulation of ATE DUT Boards for Large Pin Count Applications
    Jose MOREIRA, Baireuther ORKIDE, Merlin WALLNER, Ott MICHAEL (Advantest - Germany), Kikuchi ARITOMO, Natsuki SHIOTA (Advantest - Japan)
    Presenter Headshot
    16:00 - 17:30
    EXPO Move-out
    17:30 - 17:35
    Awards
    Jerry BROZ (SWTest Conference Chair, USA)
    17:35 - 21:00
    Japanese Street Food Festival (Olive/Garden 5th Floor)

    Poster Sessions

    Poster Session

    Session Chair: Nyi Nyi THEIN (Western Digital Corporation , Japan)

      Poster Session

      Session Chair: Nyi Nyi THEIN (Western Digital Corporation , Japan)

        Time Event
        5:30 - 15:00
        2024 SWTest Asia Charity Golf Tournament (The Classic Golf Club)
        5:30 - 6:00
        Meet at Hotel Lobby
        6:00 - 6:10
        Leave Hotel
        7:00 - 7:10
        Arrived at Classic Golf Club
        15:00 - 15:10
        Leave from Classic Golf Club
        16:00 - 16:10
        Arrived at Fukuoka Airport
        16:40 - 16:50
        Back to Hotel

        Keynote Information

        Thursday Keynote Speaker

        Speaker Headshot

        Hiroto YASUURA, PhD

        National Institute of Information - Japan

        Hiroto Yasuura is a Professor Emeritus of Kyushu University. He is also a Vice Director General (Chief Cyber Science Infrastructure Director) of National Institute of Informatics (NII).  He also serves for Ministry of Education, Culture, Sports, Science and Technology (MEXT) and Japan Science and Technology Agency (JST) as chairs of several committees. Additionally, he has worked for several local governments as advisors and private companies as independent directors.

        Prof. Yasuura received the B.E., M.E. and Ph.D. degrees in computer science from Kyoto University, Kyoto, Japan, in 1976, 1978, and 1983 respectively. He was an associate professor in Kyoto University and moved to Kyushu University in 1991 as a professor. In Kyushu University, he conducted research projects on the system LSI design methodology, which includes data-path width optimization, low-energy system design, SoC architecture and a core base LSI test method.  He also promoted education of VLSI design in computer science area in Japan with VDEC (VLSI Design and Education Center) in University of Tokyo.

        He served as the research director of Silicon-Sea-Belt Fukuoka from 2001, to build up a research-industry cluster on LSI design. More than 250 LSI design related companies moved to or were established in the Fukuoka area in the last 25 years. He is also one of the founders of ISIT (Institute of Systems, Information Technologies and Nanotechnologies, established in 1995), which is founded by Fukuoka city for promoting ICT industry.

        He served as Technical Program Chair and General Chair of ICCAD in 1997 and 1998, respectively, Vice President of IEEE CAS Society, an ACM SIGDA advisory board member, General Chair of ASP-DAC 2003, and Steering Committee Chair of ASP-DAC. He is a fellow of IEEE, IEICE (Institute of Electronics, Information and Communication Engineers) and IPSJ (Information Processing Society of Japan).

        Keynote Topic:

        Silicon Seabelt 2.0: Challenges of Kyushu for Reproduction of Silicon Island

        Kyushu was called Silicon Island in the 80’s and 90’s. With the opening of TSMC’s factory in Kumamoto, we started a new step of revitalization of the silicon island.  Leveraging integration of over 1000 companies related with semiconductor industry, we are restoring the activities on education, industrial eco-system and business environment for modern semiconductor industry. By the collaboration with Taiwan, Korea and South-East Asian countries, we have launched the project Silicon SeaBelt 2.0.

        The talk includes various activities and collaborations of Japanese central and local governments, universities in Kyushu area and industrial partners in Kyushu and foreign countries.


        Friday Keynote Speaker

        Speaker Headshot

        Shinya AKATA

        Sony Corporation - Japan

        Shinya Akata is a seasoned semiconductor professional with a strong background in test engineering and design for testability (DFT). Akata-san joined Sony Corporation in 1995 and has  held various leadership roles, including Test Engineer, DFT Engineer and Test Leader.  In 2019, he was dispatched to Sony Semiconductor Manufacturing Corporation to serve as the Senior General Manager of the CIS Test Engineering Division.  Currently, he is the Deputy Senior General Manager of the Design & System Technological Platform Division at Sony Semiconductor Solutions Corporation.

        Keynote Topic:

        Critical Role of Test for Image Sensor Development

        Image sensors have become an integral part of our modern world, powering devices from smartphones to autonomous vehicles. SONY, a pioneer in this field, has developed a global reputation for producing high-quality image sensors that deliver exceptional performance. As the person responsible for testing these critical components, I believe that a rigorous testing process is essential to ensure their reliability and functionality. In this presentation, we will discuss the critical processes that allow the next generation of devices to shine through their strengths and eliminate their weaknesses with thorough test strategies.


        Friday Keynote Speaker

        Speaker Headshot

        Tetsu OZAWA

        Socionext Inc. - Japan

        Tetsu Ozawa is the General Manager of the Production & Quality Management Group, Product Engineering Division, at Socionext Inc. Headquarters in Yokohama city, Kanagawa prefecture, Japan. His team is responsible for testing technologies and yield management for all products of Socionext.He has more than 30 years of experience in test development and test engineering and is currently responsible for test management (technologies, quality, costs, equipment, components, capabilities, delivery dates, resources). Since then, he has been involved in the outsourcing business for IDM company and fabless company for over 15 years, and now as fabless, he has win-win relationship with global eco-partners to run the outsourcing business. Socionext will continue to provide stable supply of leading-edge, high-quality SoC products to global customers through superior testing technology.

        Keynote Topic:

        New Wafer Testing Challenges for Leading-Edge SoC Products

        Socionext has built a new business model "Solution SoC" to provide SoC products to global customers seeking leading-edge and innovative chips. Socionext is focusing business on the advanced custom chips in the automotive, data center/networking and smart device markets.  At present, in the leading-edge semiconductor market, with the evolution of the advanced wafer process node, enlargement of the device, increasing high-current, and high-speed rapid advance are crucial.  In addition, leading-edge chips and packaging technologies are constantly developing, further increasing the value added to chips and assemblies.

        We believe that the expectation and importance of advanced testing technology are more profound than ever, and that we are in a period of great change. We also believe that the establishment of new testing technologies and the linkage of new semiconductor value chains will bring significant benefits, such as improved yield and quality.  In addition, it is necessary for us to adapt to flexible semiconductor process flows to make profits in various advanced products in the future.  Therefore, we are promoting the establishment of a technology to change the test in real time according to the manufacturing situation and to shift the process flow to the left or right. Among these activities, wafer testing is very significant. 

        In this article we will introduce the development status of Socionext’s leading-edge SoC, and new test technology issues and the contents of the challenges, situation, and the expectation to the test partners countries.


        Tech Showcase Program

        Thursday, October 24th, 2024

        • Tech Showcase #1
          12:25 - 12:45
          FormFactor:
        • Tech Showcase #2
          13:25 - 13:45
          MPI:
        • Tech Showcase #3
          15:35 - 15:55
          Japan Electronic Material Corp:

        Friday, October 25th, 2024

        • Tech Showcase #4
          12:25 - 12:45
          MJC
        • Tech Showcase #5
          13:25 - 13:45
          Teraprobe: