Schedule-At-A-Glance
Start |
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7:00 |
7:30 |
8:00 |
8:30 |
9:00 |
9:30 |
10:00 |
10:30 |
11:00 |
11:30 |
12:00 |
12:30 |
13:00 |
13:30 |
14:00 |
14:30 |
15:00 |
15:30 |
16:00 |
16:30 |
17:00 |
17:30 |
18:00 |
18:30 |
19:00 |
19:30 |
20:00 |
20:30 |
Poster (Grand Foyer 1st floor) |
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Poster Session |
Poster Session |
Tech Showcase (Navis C 1st Floor) |
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FormFactor: |
MPI: |
Japan Electronic Material Corp: |
EXPO (ARGOS C-F 1st Floor) |
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EXPO Move-in |
EXPO Open |
Kagamiwari Ceremony & Welcome Reception |
Start |
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7:00 |
7:30 |
8:00 |
8:30 |
9:00 |
9:30 |
10:00 |
10:30 |
11:00 |
11:30 |
12:00 |
12:30 |
13:00 |
13:30 |
14:00 |
14:30 |
15:00 |
15:30 |
16:00 |
16:30 |
17:00 |
17:30 |
18:00 |
18:30 |
19:00 |
19:30 |
20:00 |
20:30 |
21:00 |
21:30 |
Poster (Grand Foyer 1st floor) |
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Poster Session |
Poster Session |
Tech Showcase (Navis C 1st Floor) |
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MJC |
Teraprobe: |
Detailed Schedule
Time | Event |
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20:00 - 23:00 | EXPO Carry-In/Setup from 10/23 20:00 to 23:00 |
Poster Sessions
Poster Session
- Advanced DUT protection during Avalanche testing on wafer levelOndrej BETAK, Zdenek SIMERSKY (UNITES Systems a.s. - Czech Republic)
- More effective high voltage(1,000V) parametric test technique with MEMS probe cardTakao SAEKI (FormFactor Inc - Japan)
- New Cleaning Sheet filled with abrasive gel in all cells of melamine sponge.Tad ROKKAKU (Probe Innovation USA, LLC - USA)
- Towards Ultra-High Pin Count Probe Card for high end logic devicesAlice GHIDONI, Elia MISSAGLIA (Technoprobe Spa - Italy)
- Adjusting Device Temperature Measurement using a Thermocouple Probe CardHiroyuki NAKAMURA (Nidec SV Probe - Japan)
- Power supply characteristics of Printed Wiring Boards for low-voltage, high-speed device testingWai Kit K (Lincstech Co., Ltd. - Japan)
- Enhancing High-Density Semiconductor Testing with Dual-Head Laser Micro Bonding and Vacuum Gripper TechnologyGi Jung NAM, HONG CHUL KIM (DAWON NEXVIEW - South Korea)
- A Comprehensive Study on Improving Probe Card Transmission Lines for Effective High-Frequency Wafer-Level TestingAlessia GALLI, Dario VILLA (Technoprobe - Italy)
- New Flying Probe Tester for Probe CardsKoichi ANDO (HIOKI E.E. CORPORATION - Japan)
- Development of low CTE LTCC material for ST substratesTakahisa YAMAGUCHI, Eiichi NAKAMURA, Noriyuki YOSHIDA, Shigekatsu KONO (Nippon Electric Glass Co.,Ltd. - Japan)
- Introduction of precious metal alloy for Probe-pins materials and mechanical properties of Cu-Ag alloy that product name called TK-101.Tetsuya KATO, Suganuma RYOSUKE, Takada KAZUYASU (TANAKA KIKINZOKU KOGYO K.K. - Japan)
- Testing AI chips and KGD at wafer-level: A new approach for full content test in wafer probingKlemens REITINGER (ERS electronic GmbH - Germany)
- Productivity Enhancements when Drilling Guide Plates for Advanced Vertical Probe Cards - A Comparison between Nanosecond, Picosecond and Femtosecond Pulsed LasersAlan FERGUSON, Chris STOKES (Oxford Lasers - United Kingdom)
- ATE Spring Pin to DUT Board Via Interconnect: Myths and ChallengesJose MOREIRA (Advantest - Germany)
- Wafer test with simultaneous stimulation of sensor devicesGeorg FRANZ (T.I.P.S. Messtechnik GmbH - Austria)
- Process for Integrating MLOs Manufactured on Digital Lithography SystemsKsenija VARGA, R HOLLY, T UHRMANN, T ZENGER (EV Group - Austria), C LEE, Y KUO (EV Group - Taiwan), C WANG, H CHANG, L CHANG, T YANG (ITRI Industrial Technology Research Institute - Taiwan), D JANSSEN, M REYBROUCK, M VANDEVYVERE, N VAN HERCK, S VANCLOOSTER (FUJIFILM Electronic Materials (Europe) - Belgium)
- Hybrid Bonding Technology for Next-Generation 3D-IC/ChipletsTakafumi FUKUSHIMA, Fukushima TAKAFUMI (Tohoku University - Japan)
- 3D-IC Fabrication with TSV at the die level from 2D-ICJiayi SHEN, Jlayi SHEN (Tohoku University - Japan)
- Robust Classifications of WBM Defect Patterns -Multimodal approachTaiki AI, Daisuke TAKADA, Koichi SUMIYA, Sumika ARIMA, Taiki ITO, Takumi MAEDA (University of Tsukuba - Japan)
- Interaction Modeling of High-dimensional Data with the Bias and High Correlation -Sparse Factorization Machines Approach.Haruki OZAWA, Sara HOSHINO, Sumika ARIMA, Sumika WATANABE, Taiki ITO, Takuya MATSUZAWA (University of Tsukuba - Japan)
Poster Session
Time | Event | ||
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7:30 - 17:00 | Attendees Registration Check-In | ||
8:45 - 9:00 | Friday Overview Jerry BROZ (SWTest Conference Chair, USA) | ||
9:00 - 9:30 |
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9:30 - 10:00 |
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10:00 - 10:30 | Break | ||
10:00 - 10:30 | Poster Session Nyi Nyi THEIN (Western Digital Corporation , Japan) | ||
10:00 - 16:00 | EXPO Open | ||
10:30 - 12:00 | Session 4 Advancing Wafer Probing Efficiency and Quality Session Chair: Masatomo TAKAHASHI (Accretech, Japan) | ||
10:30 - 11:00 |
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11:00 - 11:30 |
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11:30 - 12:00 |
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12:00 - 14:00 | Lunch | ||
14:00 - 15:30 | Session 5 High-Speed KGD and Power Module Testing Challenges Session Chair: Alex YANG (MPI Corporation, Taiwan) | ||
14:00 - 14:30 |
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14:30 - 15:00 |
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15:00 - 15:30 |
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15:30 - 16:00 | Break | ||
15:30 - 16:00 | Poster Session Nyi Nyi THEIN (Western Digital Corporation , Japan) | ||
16:00 - 17:30 | Session 6 Probe Card MLO and PCB Design for High-Speed Session Chair: Nobuhiro KAWAMATA (FormFactor, Japan) | ||
16:00 - 16:30 |
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16:30 - 17:00 |
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17:00 - 17:30 |
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16:00 - 17:30 | EXPO Move-out | ||
17:30 - 17:35 | Awards Jerry BROZ (SWTest Conference Chair, USA) | ||
17:35 - 21:00 | Japanese Street Food Festival (Olive/Garden 5th Floor) |
Poster Sessions
Poster Session
Poster Session
Time | Event |
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5:30 - 15:00 | 2024 SWTest Asia Charity Golf Tournament (The Classic Golf Club) |
5:30 - 6:00 | Meet at Hotel Lobby |
6:00 - 6:10 | Leave Hotel |
7:00 - 7:10 | Arrived at Classic Golf Club |
15:00 - 15:10 | Leave from Classic Golf Club |
16:00 - 16:10 | Arrived at Fukuoka Airport |
16:40 - 16:50 | Back to Hotel |
Keynote Information
Thursday Keynote Speaker
Hiroto YASUURA, PhD
National Institute of Information - Japan
Hiroto Yasuura is a Professor Emeritus of Kyushu University. He is also a Vice Director General (Chief Cyber Science Infrastructure Director) of National Institute of Informatics (NII). He also serves for Ministry of Education, Culture, Sports, Science and Technology (MEXT) and Japan Science and Technology Agency (JST) as chairs of several committees. Additionally, he has worked for several local governments as advisors and private companies as independent directors.
Prof. Yasuura received the B.E., M.E. and Ph.D. degrees in computer science from Kyoto University, Kyoto, Japan, in 1976, 1978, and 1983 respectively. He was an associate professor in Kyoto University and moved to Kyushu University in 1991 as a professor. In Kyushu University, he conducted research projects on the system LSI design methodology, which includes data-path width optimization, low-energy system design, SoC architecture and a core base LSI test method. He also promoted education of VLSI design in computer science area in Japan with VDEC (VLSI Design and Education Center) in University of Tokyo.
He served as the research director of Silicon-Sea-Belt Fukuoka from 2001, to build up a research-industry cluster on LSI design. More than 250 LSI design related companies moved to or were established in the Fukuoka area in the last 25 years. He is also one of the founders of ISIT (Institute of Systems, Information Technologies and Nanotechnologies, established in 1995), which is founded by Fukuoka city for promoting ICT industry.
He served as Technical Program Chair and General Chair of ICCAD in 1997 and 1998, respectively, Vice President of IEEE CAS Society, an ACM SIGDA advisory board member, General Chair of ASP-DAC 2003, and Steering Committee Chair of ASP-DAC. He is a fellow of IEEE, IEICE (Institute of Electronics, Information and Communication Engineers) and IPSJ (Information Processing Society of Japan).
Keynote Topic:
Silicon Seabelt 2.0: Challenges of Kyushu for Reproduction of Silicon Island
Kyushu was called Silicon Island in the 80’s and 90’s. With the opening of TSMC’s factory in Kumamoto, we started a new step of revitalization of the silicon island. Leveraging integration of over 1000 companies related with semiconductor industry, we are restoring the activities on education, industrial eco-system and business environment for modern semiconductor industry. By the collaboration with Taiwan, Korea and South-East Asian countries, we have launched the project Silicon SeaBelt 2.0.
The talk includes various activities and collaborations of Japanese central and local governments, universities in Kyushu area and industrial partners in Kyushu and foreign countries.
Friday Keynote Speaker
Shinya AKATA
Sony Corporation - Japan
Shinya Akata is a seasoned semiconductor professional with a strong background in test engineering and design for testability (DFT). Akata-san joined Sony Corporation in 1995 and has held various leadership roles, including Test Engineer, DFT Engineer and Test Leader. In 2019, he was dispatched to Sony Semiconductor Manufacturing Corporation to serve as the Senior General Manager of the CIS Test Engineering Division. Currently, he is the Deputy Senior General Manager of the Design & System Technological Platform Division at Sony Semiconductor Solutions Corporation.
Keynote Topic:
Critical Role of Test for Image Sensor Development
Image sensors have become an integral part of our modern world, powering devices from smartphones to autonomous vehicles. SONY, a pioneer in this field, has developed a global reputation for producing high-quality image sensors that deliver exceptional performance. As the person responsible for testing these critical components, I believe that a rigorous testing process is essential to ensure their reliability and functionality. In this presentation, we will discuss the critical processes that allow the next generation of devices to shine through their strengths and eliminate their weaknesses with thorough test strategies.
Friday Keynote Speaker
Tetsu OZAWA
Socionext Inc. - Japan
Tetsu Ozawa is the General Manager of the Production & Quality Management Group, Product Engineering Division, at Socionext Inc. Headquarters in Yokohama city, Kanagawa prefecture, Japan. His team is responsible for testing technologies and yield management for all products of Socionext.He has more than 30 years of experience in test development and test engineering and is currently responsible for test management (technologies, quality, costs, equipment, components, capabilities, delivery dates, resources). Since then, he has been involved in the outsourcing business for IDM company and fabless company for over 15 years, and now as fabless, he has win-win relationship with global eco-partners to run the outsourcing business. Socionext will continue to provide stable supply of leading-edge, high-quality SoC products to global customers through superior testing technology.
Keynote Topic:
New Wafer Testing Challenges for Leading-Edge SoC Products
Socionext has built a new business model "Solution SoC" to provide SoC products to global customers seeking leading-edge and innovative chips. Socionext is focusing business on the advanced custom chips in the automotive, data center/networking and smart device markets. At present, in the leading-edge semiconductor market, with the evolution of the advanced wafer process node, enlargement of the device, increasing high-current, and high-speed rapid advance are crucial. In addition, leading-edge chips and packaging technologies are constantly developing, further increasing the value added to chips and assemblies.
We believe that the expectation and importance of advanced testing technology are more profound than ever, and that we are in a period of great change. We also believe that the establishment of new testing technologies and the linkage of new semiconductor value chains will bring significant benefits, such as improved yield and quality. In addition, it is necessary for us to adapt to flexible semiconductor process flows to make profits in various advanced products in the future. Therefore, we are promoting the establishment of a technology to change the test in real time according to the manufacturing situation and to shift the process flow to the left or right. Among these activities, wafer testing is very significant.
In this article we will introduce the development status of Socionext’s leading-edge SoC, and new test technology issues and the contents of the challenges, situation, and the expectation to the test partners countries.
Tech Showcase Program
Thursday, October 24th, 2024
Tech Showcase #1
12:25 - 12:45
FormFactor:
Tech Showcase #2
13:25 - 13:45
MPI:
Tech Showcase #3
15:35 - 15:55
Japan Electronic Material Corp:
Friday, October 25th, 2024
Tech Showcase #4
12:25 - 12:45
MJC
Tech Showcase #5
13:25 - 13:45
Teraprobe: